To make a semiconductor device, several layers of different types of material are deposited on a substrate, e.g., a silicon wafer. After they are deposited, those layers are processed to create devices and interconnects that form the desired integrated circuits. Many of those layers must be planarized to ensure that subsequently deposited layers will be applied to a substantially flat surface. A widely adopted planarizing technique is chemical mechanical polishing (“CMP”).
FIG. 1a illustrates a cross-section of a structure that may be formed when making a semiconductor device. That structure includes conductive layer 100 upon which is formed dielectric layer 101. Barrier layer 102 lines a via that has been etched into dielectric layer 101, and copper layer 103 is formed on barrier layer 102. A CMP step is applied to that structure to remove copper layer 103, and the underlying barrier layer, from the surface of dielectric layer 101 generating the structure shown in FIG. 1b. 
Current methods for controlling the CMP process rely on modifying slurry composition and polishing pad properties. Changes to the slurry composition and/or the polishing pad may not, however, enable the polish rate, or the selectivity of that rate across different layers, to be optimized. Taking the example illustrated in FIGS. 1a and 1b, to produce the structure shown in FIG. 1b requires polishing through copper layer 103, then through barrier layer 102. Because copper is a relatively soft metal, it will polish at a relatively high rate, when compared to the rate at which barrier layer 102 (typically made from a relatively hard material like tantalum or tantalum nitride) is polished. When continuing to polish the structure after breaking through copper layer 103 to barrier layer 102, differences in selectivity of the polishing process to those two layers can cause significant dishing of wide features.
Such differences in selectivity may be a significant concern, when making damascene based structures. To make such structures, low selectivity between the primary metal (e.g., copper) and the underlying barrier layer (e.g., tantalum or tantalum nitride) is required; whereas, high selectivity must be maintained between those materials and the underlying dielectric layer to stop the CMP process on that layer. Optimally, the relative selectivity of the polishing process to the primary metal and the barrier layer is about 1:1; whereas, the relative selectivity to those materials, when compared to the dielectric layer, is about 100:1, or greater. Maintaining such a high degree of selectivity between the primary metal/barrier layer and the dielectric layer may be difficult, when such a layer is formed from polymer based, carbon based or porous low k dielectrics, as such materials are not as strong as silicon dioxide.
Accordingly, there is a need for an improved CMP apparatus that enables better control of the polishing rate and the selectivity of the polish rate across different layers. There is a need for such an apparatus that enables higher throughput for the CMP process. The present invention provides such an apparatus.